The present invention relates generally to a clock multiplier circuit. More specifically, the invention relates to a clock multiplier circuit suitably used for generating a high frequency clock signal having small jitters from a low frequency input clock signal.
FIG. 1 is a circuit diagram showing a conventional digital phase locked loop (which will be hereinafter referred to PLL) circuit (see the Japanese Official Gazette of Patent Application Laid-Open No. 9-238072). The digital PLL circuit of FIG. 1 comprises: a 1/M divider 1 for dividing a reference clock signal by M; a frequency comparator circuit 2 for comparing the frequencies of outputs of the 1/M divider 1 and a 1N divider 7; a delay control circuit 3 for controlling a delayed value of a ring oscillator on the basis of information from the frequency comparator circuit 2; the ring oscillator 4 comprising a delay variable circuit 5 and an inverter 6, which are capable of changing the delayed value on the basis of control information from the delay control circuit 3; and the 1/N divider 7 for dividing an output clock signal of the ring oscillator by N.
The frequency comparator circuit 2 counts the numbers of pulses of two input clock signals from the 1/M divider 1 and the 1/N divider 7, by means of a counter, and compares the frequencies of the two clock signals on the basis of magnitude of the counted numbers. The delay control circuit 3 controls the delayed value of the ring oscillator 4 on the basis of information of the frequency comparator circuit 2 so that the clock frequency of the ring oscillator 4 divided by N is equal to the clock frequency obtained by dividing the frequency clock frequency by M.
However, in the conventional digital PLL circuit, there is a problem in that it is difficult to increase a multiplication factor.
For example, it is assumed that the reference clock signal has a frequency of 32 KHz, and the digital PLL output clock signal has a frequency of 32 MHz, the multiplication factor being 1000, the dividing value M of the divider 2 being 1, and the dividing value N of the divider 7 being 1000. Usually, the frequency comparator circuit 2 can not accurately compare frequencies unless a counter of at least 10 bits counts 1000. On the other hand, when the number of counted pulses of the digital PLL output clock signal is 1000, the number of counted pulses of the input clock signal to the frequency comparator circuit 2 from the 1/N divider 7 is 1. Therefore, one comparing operation can not be carried out unless the number of counted pulses of the digital PLL output clock signal is 1000000(=1000.times.1000).
Thus, the frequency comparison needs such a large counted value. Therefore, in the conventional circuit, which can compare frequencies only one time per about 1000000 counts, there is a problem in that the speed of response is too slow so that jitters are increased, since the frequency of the stable ring oscillator fluctuates in accordance with external voltage, temperature and so forth. In addition, in the lock-in time to lock the PLL circuit, it is required to compare frequencies at least ten times, so that it takes at least few seconds. Therefore, there is also a problem in that it is not allowable.